Memory devices are used to store massive digital information. Over the past several years, advances in processes and techniques and market demands have given rise to increasing diversification of memory device species. Among the variety of existing memory devices, flash memories are developing particularly fast and have found extensive application because they can maintain the stored information for a long time without power supply, in addition to other many advantages including high integration, fast access, and ease of erasing and rewriting.
A flash memory is comparable in basic structure to a MOS transistor including a source, a drain and a gate (control gate, CG) except that the flash memory further includes a floating gate (FG). The FG of the flash memory is located between the control gate and a conductive channel so as to be isolated from all other electrodes. Due to the presence of the floating gate, the flash memory can be controlled to perform three basic operations: programming, reading; and erasing.
In general, flash memory can be divided by their gate structure into stacked-gate ones and split-gate ones. Split-gate flash memories are widely used because of their low programming voltages, high programming efficiency and effective avoidance of over-erasing.
FIG. 1 schematically illustrates the architecture of a conventional split-gate flash memory. As shown in FIG. 1, the split-gate flash memory 100 includes: a semiconductor substrate 101; a source line 102 and a drain line 103, serving as bit lines (BLs) and extending on the semiconductor substrate 101 at a certain interval; and a word line (WL) 104 formed above the semiconductor substrate 101 between the source line 102 and the drain line 103. A word-line oxide layer 105 is formed between the word line 104 and the semiconductor substrate 101. A first memory bit cell 110 and a second memory bit cell 120 having the same structure are disposed on opposing sides of the word line 104. With the first memory bit cell 110 as an example, it includes a floating-gate oxide layer 106 on the surface of the semiconductor substrate 101, a floating gate 107 resting on the floating-gate oxide layer 106, a control-gate dielectric layer 108 on the floating gate 107 and a control gate 109 on the control-gate dielectric layer 108. The floating gate 107 and the word line 104 are intervened by a tunneling oxide layer 111. With suitable voltages applied on the source line 102, the drain line 103, the word line 104 and the control gate 108, the split-gate flash memory 100 can be controlled to perform program, read and erase operations.
In continuation of the example illustrated in FIG. 1, on the one hand, during an erase operation of the split-gate flash memory 100, electrons in the floating gate 107 will travel through the tunneling oxide layer 111 into the word line 104. An overlap between the floating gate 107 and the word line 104 (marked by a dotted line circle A in FIG. 1) determines a coupling ratio between the floating gate 107 and the word line 104. As long as the tunneling is enabled, the lower the coupling ratio is, the stronger an electric field is created between the floating gate 107 and word line 104 under the same conditions, and the better the erasing performance will be. In other words, within a certain range, reducing the overlap between the word line 104 and the floating gate 107 is conducive to the erasing efficiency.
On the other hand, the continuous enhancement in the integration of semiconductor components is bringing about increasing miniaturization of split-gate flash memories, fabricating short-channel effect suppression more and more important to leakage control. However, in order to account for a channel resistance induced by the word line, the conventional split-gate flash memory 100 has to maintain a relative high voltage (usually higher than 4 V) on the word line and a rather great thickness (about 100 Å to 200 Å) of the word-line oxide layer 105. Additionally, the coupling between the word line 104 and the floating gate 107 can lower a word line-induced barrier, causing increased channel leakage currents and a considerable short-channel effect. This may hinder the mass production of the split-gate flash memory.
Therefore, it is necessary for the conventional split-gate flash memory to be further improved in terms of structure and control.